UT52L1616MC-7 查看數據表（PDF） - Utron Technology Inc
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UT52L1616MC-7 Datasheet PDF : 36 Pages
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UTRON
Preliminary Rev. 0.91
UT52L1616
1M X 16 BIT SDRAM
Current state CE RAS CAS WE Address
Command
Operation
Write with auto H X
X
X
X
DESL
Continue burst to end and
precharge
precharge
LH
H
H
X
NOP
Continue burst to end and
precharge
LH
H
L
X
BST
ILLEGAL
LH
L
H
BA,CA,A10 READ/READ A ILLEGAL
LH
L
L
BA,CA,A10 WRIT/WRIT A ILLEGAL
LL
H
H
BA,RA
ACT
Other bank active; ILLEGAL on
same bank*³
LL
H
L
BA,A10
PRE,PALL
ILLEGAL
LL
L
H
X
REF,SELF
ILLEGAL
LL
L
L
MODE
MRS
ILLEGAL
Refresh
HX
X
X
X
DESL
Enter IDLE after tRC
(auto refresh) L H
H
H
X
NOP
Enter IDLE after tRC
LH
H
L
X
BST
Enter IDLE after tRC
LH
L
H
BA,CA,A10 READ/READ A ILLEGAL
LH
L
L
BA,CA,A10 WRIT/WRIT A ILLEGAL
LL
H
H
BA,RA
ACT
ILLEGAL
LL
H
L
BA,A10
PRE,PALL
ILLEGAL
LL
L
H
X
REF,SELF
ILLEGAL
LL
L
L
MODE
MRS
ILLEGAL
Notes
H: VIH. L: VIL. x:VIH or VIL.
1. The other combinations are inhibit.
2. An interval of tRWL is required between the final valid data input and the precharge command.
3. If tRRD is not satisfied, other bank active command is illegal.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
9
P90004
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