UT62V25716BS-70LL 查看數據表（PDF） - Utron Technology Inc
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UT62V25716BS-70LL Datasheet PDF : 10 Pages
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Rev. 1.0
UTRON
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled) (1,2,4)
UT62V25716
256K X 16 BIT LOW POWER CMOS SRAM
tRC
Address
DOUT
tAA
tOH
tOH
Data Valid
READ CYCLE 2 ( CE1and CE2 and OE Controlled) (1,3,5,6)
t RC
Address
CE1
t AA
t ACE1
CE2
t ACE2
LB , UB
t BLZ
OE
t CLZ1
t OE
t CLZ2
Dout
HIGH-Z
t OLZ
t OH
t CHZ1
t CHZ2
t OHZ
Data Valid
HIGH-Z
t BHZ
Notes :
1. WE is HIGH for read cycle.
2. Device is continuously selected CE1 =VIL and CE2=VIH. and LB =VIL and UB =VIH.
3. Address must be valid prior to or coincident with CE1 and CE2 and LB and UB transition; otherwise tAA is the limiting
parameter.
4. OE is low.
5. tCLZ1, tCLZ2, tOLZ, tCHZ1, tCHZ2 and tOHZ are specified with CL=5pF. Transition is measured ± 500mV from steady state.
6. At any given temperature and voltage condition, tCHZ1 is less than tCLZ1, tCHZ2 is less than tCLZ2, tOHZ is less than tOLZ.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
4
P80065
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