CS4812 查看數據表（PDF） - Cirrus Logic
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CS4812 Datasheet PDF : 36 Pages
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CS4812
SWITCHING CHARACTERISTICS - CONTROL PORT - I2C® SLAVE
(TA = 25 °C; VA, VD = 5 V; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 30 pF)
Parameter
Symbol
Min
Max
Units
I2C® Slave Mode (SPI/I2C = 1, SCPM/S = 0) (Note 17)
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
SCL Low Time
SCL High Time
RST rising to start condition
(Note18)
SDA Hold Time from SCL Falling
(Note 19)
Rise Time of Both SDA and SCL
Fall Time of Both SDA and SCL
SCL Falling to CS4812 ACK
SCL Falling to SDA Valid During READ
Time from SCL Rising to REQ Rising
(Note 20)
Rise Time for REQ
Fall Time for REQ
Setup Time for Stop Condition
Setup Time for Repeated Start
fscl
tbuf
thdst
tlow
thigh
tsrs
thdd
tr
tf
tsca
tscsdv
tscrh
trr
trf
tsusp
tsust
-
100
kHz
4.7
-
µs
4.0
-
µs
4.7
-
µs
4.0
-
µs
1
-
ms
0
-
µs
-
1
µs
-
300
ns
-
1.3
µs
-
1.5
µs
-
2*DSPCLK+10 ns
-
100
ns
-
100
ns
4.7
-
µs
4.7
µs
Notes: 17. Use of the I2C bus interface requires a license from Philips. I2C is a registered trademark of Philips
Semiconductors.
18. Not tested.
19. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
20. DSPCLK frequency is twice the DSP instruction rate.
10
DS291PP3
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