CS4812 查看數據表（PDF） - Cirrus Logic

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CS4812

Fixed Function Multi-Effects Audio Processor

Cirrus Logic 

CS4812

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI SLAVE

(TA = 25 °C; VA, VD = 5 V; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 30 pF)

Parameter

Symbol

Min

Max

SPI Slave Mode (SPI/I2C = 0, SCPM/S = 0, Note 14)

CCLK Clock Frequency

CCLK Low Time

CCLK High Time

Rise Time of Both CDIN and CCLK Lines

Fall Time of Both CDIN and CCLK Lines

Setup Time CDIN to CCLK Rising

Hold Time CCLK Rising to CDIN

(Note 11)

Time from CCLK edge to CDOUT Valid

(Note 12)

Rise Time for CDOUT

Fall Time for CDOUT

CS Falling to CCLK Rising

Time from CCLK Falling to CS Rising

High Time Between Active CS

Time from CCLK Rising to REQ Rising

(Note 13)

Rise Time for REQ

Fall Time for REQ

fsck

tscl

tsch

tr

tf

tcdisu

tcdih

tscdov

tcdor

tcdof

tcss

tsccsh

tcsht

tscrh

trr

trf

-

6

66

-

66

-

-

100

-

100

40

-

15

-

-

45

-

25

-

25

20

-

0

-

1

-

-

2*DSPCLK+10

-

100

-

100

Notes: 11. Data must be held for sufficient time to bridge 100 ns transition time of CCLK.

12. CDOUT should NOT be sampled during this time period.

13. DSPCLK frequency is twice the DSP instruction rate.

14. Timing is guaranteed by characterization. Production test guarantees functionality.

Unit

MHz

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

µs

ns

ns

ns

DS291PP3

7

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