STA020DJTR 查看數據表（PDF） - STMicroelectronics

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STA020DJTR

96 kHz digital audio interface transmitter

STMicroelectronics 

Overview

STA020

Note:

Table 3. Pin description (continued)

N°

Pin

Function

Emphasis 0/Channel status bit 9.

14

EM0/C9

In professional mode, EM0 and EM1 encode channel status bits 2, 3

and 4. In consumer mode, C9 is the inverse of channel status bit 9 (bit 1

of byte 1). EM0/C9 are ignored in transparent mode.

Channel status block output/Subcode bit clock.

15

CBL/SBC In professional and consumer modes, the channel status block output

is high for the first 15 bytes of channel status. In CD mode, this pin

outputs the subcode bit clock.

Master reset.

16

RST

When low, all internal counters are reset.

Transparent mode/Frequency control 1.

In professional mode, setting TRNPT low selects normal operation &

CBL is an output. Setting TRNPT high allows the STA020 to be

24

TRNPT/FC1 connected directly to an STA120. In transparent mode, CBL is an input

& MCK must be at 256 Fs. In consumer mode, FC0 and FC1 are

encoded versions of channel status bits 24 and 25. When FC0 and FC1

are both high, CD mode is selected.

Transmitter interface

5

20, 17

MCK

TXP, TXN

Master clock. Clock input at 128x the sample frequency which defines

the transmit timing. In transparent mode MCK must be 256 Fs.

Differential line drivers.

Symbol

Table 4. Digital characteristics (Tamb = 25°C; VD+ = 3.3 V 10%)

Parameter

Test condition

Min. Typ. Max. Unit

VIH

VIL

VOH

VOL

Iin

MCK

High-level input voltage

Low-level input voltage

High-level output voltage IO = 200 μA

Low-level output voltage

Input leakage current

Master clock frequency

Master clock duty cycle

IO = 3.2 mA

(Note: 1)

(high time/cycle time)

2.0

VDD+0.

3

V

-0.3

+0.8 V

VDD-

1.0

V

0.4

V

1.0 10

A

26 MHz

40

60

%

1. MCK must be 128x the input word rate, except in transparent mode where MCK is 256x

the input word rate.

4/15

DocID006832 Rev 7

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