P4C1981-10JC 查看數據表（PDF） - Performance Semiconductor

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P4C1981-10JC

ULTRA HIGH SPEED 16K x 4 CMOS STATIC RAMS

Performance Semiconductor 

WRITE CYCLE NO. 2 (WE CONTROLLED)(13,14)

P4C1981/1981L, P4C1982/1982L

(15)

t WC

ADDRESS

CE1, CE2

WE

DATA IN

DATA OUT

P4C1982

DATA OUT

P4C1981

tCW

t AW

t WP

t AH

t AS

DATA UNDEFINED

(9)

t WZ

tDW

DATA VALID

tDH

t

(9,14)

OW

t AWE

HIGH IMPEDANCE

t ADV

DATA VALID

1520 08

WRITE

CYCLE

NO.

3

(CE1,

CE

2

CONTROLLED)(11,12)

(15)

t WC

ADDRESS

CE1, CE2

WE

DATA IN

t AS

t CW

t AW

t WP

t DW

DATA VALID

DATA OUT

P4C1982

DATA OUT

P4C1981

HIGH IMPEDANCE tADV

t AH

t WR

t DH

DATA VALID

HIGH

IMPEDANCE

Notes:

12. CE (CE1, CE2and WE must be LOW for WRITE cycle.

13. OE is LOW for WRITE cycle.

14.

If

CE

1

or

CE

2

goes HIGH simultaneously with WE HIGH,

theoutput remains in a high impedance state.

15. Write Cycle Time is measured from the last valid address to the

first transitioning address.

87

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