CL7256S 查看數據表（PDF） - Clear Logic

零件编号

产品描述 (功能)

比赛名单

CL7256S

Laser Processed Logic Device Family

Clear Logic 

CL7256E and CL7256S Laser Processed Logic Devices

Macrocell Diagram

Local Array

Product

Term

Select

Matrix

Global Global

Clear Clocks

2

Parallel Logic

Expanders

Fast Input Configurable

Select

Register

Register

Bypass

Clock/

Enable

Select

Clear VCC

Select

D PRN Q

ENA

CLRN

from

I/O pin

to I/O

Control

Block

36 Signals 16 Expander

from LIA Product Terms

Shared Logic

Expanders

to LIA

7K drw 01

Pin Configuration

Pin Name

INPUT/GCLK1

INPUT/GCLRn

INPUT/OE1

INPUT/OE2/GCLK2

TDI

TMS

TCK

TDO

GND

VCCINT

VCCIO

NC (No Connect)

Total user I/O pins

160 pin PQFP

139

208 pin RQFP/PQFP

184

141

182

140

183

142

181

146

176

23

127

98

30

135

189

3, 18, 32, 47, 57, 64, 66, 81, 96, 111, 14, 32, 50, 72, 75, 82, 94, 116, 134,

126, 138, 143, 148

152, 174, 180, 185, 200

56, 65, 137, 144

74, 83, 179, 186

10, 25, 40, 55, 74, 89, 103, 118, 133, 5, 23, 41, 63, 85, 107, 125, 143, 165,

155

191

-

1, 2, 51, 52, 53, 54, 103, 104, 105,

106, 155, 156, 157, 158, 207, 208

128

160

7256 tbl 01

Page 5

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