CL7256S 查看數據表（PDF） - Clear Logic
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CL7256S Datasheet PDF : 16 Pages
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CL7256E and CL7256S Laser Processed Logic Devices
AC Electrical Specifications cont.
External Timing Parameters
Symbol
Parameter
Conditions
tPD1 Input to non-registered output
CL = 35 pF
tPD2 I/O input to non-registered output
CL = 35 pF
tSU
Global clock setup time
tH
Global clock hold time
tFSU Global clock setup time of fast input
tFH
Global clock hold time of fast input
tCO1 Global clock to output delay
CL = 35 pF
tCH
Global clock high time
tCL
Global clock low time
tASU Array clock setup time
tAH
Array clock hold time
tACO1 Array clock to output delay
CL = 35 pF
tACH Array clock high time
tACL
Array clock low time
tODH Output data hold time after clock
CL = 35 pF
tCNT Minimum global clock period
fCNT Maximum internal global clock frequency
tACNT Minimum array clock period
fACNT Maximum internal array clock frequency
Speed: -12P
Min Max
12.0
12.0
7.0
0.0
3.0
0.0
6.0
4.0
4.0
3.0
4.0
12.0
5.0
5.0
1.0
11.0
90.9
11.0
90.9
Speed: -12
Min Max
12.0
Unit
ns
12.0 ns
10.0
ns
0.0
ns
3.0
ns
0.0
ns
6.0
ns
4.0
ns
4.0
ns
4.0
ns
4.0
ns
12.0 ns
5.0
ns
5.0
ns
1.0
ns
11.0 ns
90.9
MHz
11.0 ns
90.9
MHz
7K tbl 06E2
Page 9
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