DESCRIPTION
The M54/74HC107 is a high speed CMOS DUAL JK FLIPFLOP fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. These flip-flop are edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Each one has independent J, K, CLOCK, and CLEAR input and Q and Q outputs. CLEAR is independent of the clock and accomplished by a logic low on the input. All inputs are equipped with protection circuits against static discharge and transient excess voltage.

. HIGH SPEED
   fMAX = 75 MHz (TYP.) AT VCC = 5 V
. LOW POWER DISSIPATION
   ICC = 2 µA (MAX.) AT TA = 25°C
. HIGH NOISE IMMUNITY
   VNIH = VNIL = 28 % VCC (MIN.)
. OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS
. SYMMETRICAL OUTPUT IMPEDANCE
  |IOH|= IOL = 4 mA (MIN.)
. BALANCED PROPAGATION DELAYS
tPLH = tPHL
. WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V
. PIN AND FUNCTION COMPATIBLE WITH 54/74LS107