General Description
The 74F273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously.

FEATUREs
■Ideal buffer for MOS microprocessor or memory
■Eight edge-triggered D-type flip-flops
■Buffered common clock
■Buffered, asynchronous Master Reset
■See 74F377 for clock enable version
■See 74F373 for transparent latch version
■See 74F374 for 3-STATE version