General description
The 74HC4024 is a high-speed Si-gate CMOS device and is pin compatible with the 4024 of the 4000B series. The 74HC4024 is specified in compliance with JEDEC standard no. 7A.
The 74HC4024 is a 7-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and seven fully buffered parallel outputs (Q0 to Q6). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle flip-flop.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.

FEATUREs and benefits
■ Low-power dissipation
■ Complies with JEDEC standard no. 7A
■ ESD protection:
   ◆ HBM JESD22-A114F exceeds 2000 V
   ◆ MM JESD22-A115-A exceeds 200 V.
■ Multiple package options
■ Specified from 40 C to +80 C and from 40 C to +125 C.

APPLICATIONs
■ Frequency dividing circuits
■ Time delay circuits.