Description
This device each contains an 8-bit binary counter that feeds an 8-bit storage register. The storage register has parallel outputs. Separate clocks are provided for both the binary counter and storage register. The binary counter features a direct clear input CCLR and a count enable input C CKEN. For cascading a ripple carry output R CO is provided. Expansion is easily accomplished by tying R CO of the first stage to CCKEN of the second stage, etc.
Both the counter and register clocks are positive-edge triggered. If the user wishes to connect both clocks together, the counter state will always be one count ahead of the register, Internal circuitry prevents clocking from the clock enable.

FEATUREs
• High Speed Operation: tpd (RCK to Q) = 18.5 ns typ (CL = 50 pF)
• High Output Current: Fanout of 15 LSTTL Loads
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)