GENERAL DESCRIPTION
The ADP1754/ADP1755 are low dropout (LDO) CMOS linear regulators that operate from 1.6 V to 3.6 V and provide up to 1.2  A of output current. These low VIN/VOUT LDOs are ideal for regulation of nanometer FPGA geometries operating from 2.5 V down to 1.8 V I/O rails, and for powering core voltages down to 0.75 V. Using an advanced proprietary architecture, the ADP1754/
ADP1755 provide high power supply rejection ratio (PSRR) and low noise, and achieve excellent line and load transient response with only a small 4.7 µF ceramic output capacitor.

FEATURES
Maximum output current: 1.2 A
Input voltage range: 1.6 V to 3.6 V
Low shutdown current: <2 µA
Very low dropout voltage: 105 mV @ 1.2 A load
Initial accuracy: ±1%
Accuracy over line, load, and temperature: ±2%
7 fixed output voltage options with soft start 0.75 V to 2.5 V (ADP1754)
Adjustable output voltage option with soft start 0.75 V to 3.3 V (ADP1755)
High PSRR
   65 dB @ 1 kHz
   65 dB @ 10 kHz
   54 dB @ 100 kHz
23 μV rms at 0.75 V output
Stable with small 4.7 µF ceramic output capacitor
Excellent load and line transient response
Current-limit and thermal overload protection
Power-good indicator
Logic-controlled enable
Reverse current protection