GENERAL DESCRIPTION
The Am79C976 controller is a highly-integrated 32-bit full-duplex, 10/100-Megabit per second (Mbps) Ethernet controller solution, designed to address high performance system application requirements. It is a flexible bus mastering device that can be used in any application, including network-ready PCs and bridge/router designs. The bus master architecture provides high data throughput and low CPU and system bus utilization. The Am79C976 controller is fabricated with advanced low-power 3.3-V CMOS process to provide low operating current for power sensitive applications.
DISTINCTIVE CHARACTERISTICS
■ Integrated Fast Ethernet controller for the
Peripheral Component Interconnect (PCI) bus
— 32-bit glueless PCI host interface
— Supports PCI clock frequency from DC to
33 MHz independent of network clock
— Supports network operation with PCI clock
from 15 MHz to 33 MHz
— High performance bus mastering
architecture with integrated Direct Memory
Access (DMA) Buffer Management Unit for
low CPU and bus utilization
— PCI specification revision 2.2 compliant
— Supports PCI Subsystem/Subvendor
ID/Vendor ID programming through the
EEPROM interface
— Supports both PCI 3.3-V and 5.0-V signaling
environments
— Plug and Play compatible
— Uses advanced PCI commands (MWI, MRL,
MRM)
— Optionally supports PCI bursts aligned to
cache line boundaries
— Supports big endian and little endian byte
alignments
— Implements optional PCI power management
event (PME) pin
— Supports 40-bit addressing (using PCI Dual
Address Cycles)
■ Media Independent Interface (MII) for
connecting external 10/100 megabit per second
(Mbps) transceivers
— IEEE 802.3-compliant MII
— Intelligent Auto-Poll™ external PHY status
monitor and interrupt
— Supports both auto-negotiable and non auto
negotiable external PHYs
— Supports 10BASE-T, 100BASE-TX/FX,
100BASE-T4, and 100BASE-T2 IEEE 802.3-
compliant MII PHYs at full- or half-duplex
■ Full-duplex operation supported with
independent Transmit (TX) and Receive (RX)
channels
■ Includes support for IEEE 802.1Q VLANs
— Automatically inserts, deletes, or modifies
VLAN tag
— Optionally filters untagged frames
■ Provides optional flow control features
— Recognizes and transmits IEEE 802.3x MAC
flow control frames
— Asserts collision-based back pressure in
half-duplex mode
■ Provides internal Management Information
Base (MIB) counters for network statistics
■ Supports PC97, PC98, PC99, and Net PC
requirements
— Implements full OnNow features including
pattern matching and link status wake-up
— Implements Magic Packet™ mode
— Magic Packet mode and the physical address
loaded from EEPROM at power up without
requiring PCI clock
— Supports PCI Bus Power Management
Interface Specification Version 1.1
— Supports Advanced Configuration and
Power Interface (ACPI) Specification Version
1.0
— Supports Network Device Class Power
Management Specification Version 1.0
■ Large independent external TX and RX FIFOs
— Supports up to 4 megabytes (Mbytes)
external SSRAM for RX and TX frame storage
— Programmable FIFO watermarks for both
transmit and receive operations
— Receive frame queuing for high latency PCI
bus host operation
— Programmable allocation of buffer space
between transmit and receive queues (Continue ...)