CP701 数据手册 ( 数据表 ) - Central Semiconductor
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CP701
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Central Semiconductor
PROCESS DETAILS
Process EPITAXIAL PLANAR
Die Size 26 x 26 MILS
Die Thickness 9.0 MILS
Base Bonding Pad Area 6.1 x 4.9 MILS
Emitter Bonding Pad Area 5.2 x 5.2 MILS
Top Side Metalization Al - 30,000Å
Back Side Metalization Au - 18,000Å
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Small Signal Transistors PNP - High Voltage Transistor Chip ( Rev : 2005 )
Central Semiconductor
Small Signal Transistors PNP - High Voltage Transistor Chip ( Rev : 2005 )
Central Semiconductor
Small Signal Transistor PNP - High Voltage Transistor Chip ( Rev : 2002 )
Central Semiconductor
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