Functional Description
The CY7C1316V18/CY7C1318V18/CY7C1320V18 are 1.8V Synchronous Pipelined SRAM equipped with DDR-II (Double Data Rate) architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter.

FEATUREs
• 18-Mb density (2M x 8, 1M x 18, 512K x 36) — Supports concurrent transactions
• 250-MHz clock for high vandwidth
• Two-word burst for reducing address bus frequency
• Double Data Rate (DDR) interfaces (data transferred at 500 MHz) @ 250 MHz
• Two input clocks (K and K) for precise DDR timing — SRAM uses rising edges only
• Two output clocks (C and C) accounts for clock skew and flight time mismatches
• Echo clocks (CQ and CQ) simplify data capture in high speed systems
• Synchronous internally self-timed writes
• 1.8V core power supply with HSTL inputs and outputs
• Variable drive HSTL output buffers
• Expanded HSTL output voltage (1.4V–VDD)
• 13x15 mm 1.0-mm pitch fBGA package, 165 ball (11x15 matrix)
• JTAG interface
• On-chip Delay Lock Loop (DLL)