Functional Description
The CY7C1351G is a 3.3 V, 128 K × 36 synchronous flow-through burst SRAM designed specifically to support unlimited true back-to-back read/write operations without the insertion of wait states. The CY7C1351G is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent write-read transitions.

FEATUREs
■ Can support up to 133-MHz bus operations with zero wait states
   ❐ Data is transferred on every clock
■ Pin compatible and functionally equivalent to ZBT™ devices
■ Internally self-timed output buffer control to eliminate the need to use OE
■ Registered inputs for flow-through operation
■ Byte write capability
■ 128 K × 36 common I/O architecture
■ 2.5 V/3.3 V I/O power supply (VDDQ)
■ Fast clock-to-output times
   ❐ 6.5 ns (for 133-MHz device)
■ Clock enable (CEN) pin to suspend operation
■ Synchronous self-timed writes
■ Asynchronous output enable
■ Available in Pb-free 100-pin TQFP package
■ Burst capability – linear or interleaved burst order
■ Low standby power