4-Mbit (256Kx18) Pipelined SRAM with NoBL™ Architecture

FEATUREs
• Pin compatible and functionally equivalent to ZBT™ devices
• Internally self-timed output buffer control to eliminate
   the need to use OE
• Byte Write capability
• 256K x 18 common I/O architecture
• Single 3.3V power supply
• 2.5V / 3.3V I/O Operation
• Fast clock-to-output times
• 2.6 ns (for 250-MHz device)
• 2.8 ns (for 200-MHz device)
• 3.5 ns (for 166-MHz device)
• 4.0 ns (for 133-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Asynchronous output enable (OE)
• Pb-Free 100 TQFP package
• Burst Capability—linear or interleaved burst order
• ZZ” Sleep Mode Option and Stop Clock option