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DDU8C3-5012A1 数据手册 ( 数据表 ) - Data Delay Devices

DDU8C3 image

零件编号
DDU8C3-5012A1

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FUNCTIONAL DESCRIPTION
The DDU8C3-series device is a 5-tap digitally buffered delay line. The signal input (IN) is reproduced at the outputs (T1-T5), shifted in time by an amount determined by the device dash number (See Table). For dash numbers 5020 and above, the total delay of the line is measured from IN to T5, and the nominal tap-to-tap delay increment is given by one-fifth of the total delay. For dash numbers below 5020, the total delay is measured from T1 to T5, and the delay increment is given by one-fourth of the total delay.


FEATURES
• Five equally spaced outputs
• Fits standard 8-pin DIP socket
• Low profile
• Auto-insertable
• Input & outputs fully CMOS interfaced & buffered
• 10 T2L fan-out capability

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零件编号
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5-TAP, 3.3V CMOS-INTERFACED FIXED DELAY LINE (SERIES DDU8C3)
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5-TAP, ECL-INTERFACED FIXED DELAY LINE
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5-TAP, TTL-INTERFACED FIXED DELAY LINE
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5-TAP, TTL-INTERFACED FIXED DELAY LINE
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5-TAP, HCMOS-INTERFACED FIXED DELAY LINE
Data Delay Devices
5-TAP, HCMOS-INTERFACED FIXED DELAY LINE
Data Delay Devices
5-TAP, ECL-INTERFACED FIXED DELAY LINE
Data Delay Devices
5-TAP, TTL-INTERFACED FIXED DELAY LINE
Data Delay Devices
5-TAP, HCMOS-INTERFACED FIXED DELAY LINE
Data Delay Devices
5-TAP, ECL-INTERFACED FIXED DELAY LINE
Data Delay Devices

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