FEATURES
• 128Mb x8, 64Mb x16 Organization
• Supports most DDR4 features
• Page size of 1024 bits for x8, 2048 bits for x16
• VDD = VDDQ = 1.2v
• VPP = 2.5V
• Operating Temperature of 0˚C to 85 ˚C
• 667MHz clock frequency (fCK)
• On-Device Termination
• Multipurpose register READ and WRITE capability
• Per-Device addressability (PDA)
• Connectivity Test
• On-Chip DLL aligns DQ, DQS, DQS transition with CK transition
• Burst lengths of 8 addresses
• All addresses and control inputs are latched on rising edge of the clock
• Bit Error Rate (BER) = 1 x 10-11
• Data Retention = 3 months at 70°C
• Cycle Endurance = 1 x 1010
• Standard FBGA package options (Pb-free):
• 78-ball (10mm x 13mm) package (x8)
• 96-ball (10mm x 13mm) package (x16)
• Timing – cycle time:
   • 1.5ns @ CL = 10 (ST-DDR4 1333)
   • 1.5ns @ CWL = 9 (ST-DDR4 1333)