GENERAL DESCRIPTION
The device is an 8Gb SLC NAND Flash memory, which is stacked by two 4Gb chips for some special operations and applications. NAND Flash devices include an asynchronous data interface for high-performance I/O operations. These devices use a highly multiplexed 8-bit bus (I/Ox) to transfer commands, address, and data. There are five control signals used to implement the asynchronous data interface: CE#, CLE, ALE, WE#, and RE#. Additional signals control hardware write protection and monitor device status (R/B#). 
This hardware interface creates a low pin-count device with a standard pinout that remains the same from one density to another, enabling future upgrades to higher densities with no board redesign.

FEATURES
• Density
   ― 8 Gb (4 Gb x 2)
• Operating voltage range
   ― VCC: 2.7–3.6V
• Open NAND Flash Interface (ONFI) 1.0-compliant1
• Single-level cell (SLC) technology
• Organization (For each 4Gb device)
   ― Page size: 4352 bytes (4096 + 256 bytes)
   ― Block size: 64 pages
   ― Plane size: 2048 blocks
• Asynchronous I/O performance
   ― tRC/tWC: 25ns
• Array performance
   ― Read page: 115µs (MAX) with on-die ECC enabled
   ― Read page: 25µs (MAX) with on-die ECC disabled
   ― Program page: 200µs (TYP) with on-die ECC
       disabled
   ― Program page: 240µs (TYP) with on-die ECC enabled
   ― Erase block: 2ms (TYP)
• Command set: ONFI NAND Flash protocol
• Advanced command set
   ― Program page cache mode
   ― Read page cache mode
   ― Permanent block locking (blocks 47:0)
   ― One-time programmable (OTP) mode
   ― Block lock
• Operation status byte provides software method for
   detecting
   ― Operation completion
   ― Pass/Fail condition
   ― Write-protect status
• Ready/Busy# (R/B#) signal provides a hardware method
   of detecting operation completion
• WP# signal: Write protect entire device
• ECC: 8-bit internal ECC is disabled at default2. It can be
   toggled using the SET FEATURE command
• Blocks 0 is valid when shipped from factory with ECC. For
   minimum required ECC, see Error Management.
• RESET (FFh) required as first command after power- on.
• Internal data move operations supported within the plane
   from which data is read
• Quality and reliability
   ― Endurance: 100,000 PROGRAM/ERASE cycles
   ― Data retention: JESD47G-compliant; see qualification
      report
   ― Additional: Uncycled data retention: 10 years 24/7 @
      70°C
   ― Read unique ID
   ― Internal data move
   ― Programmable drive strength