Functional Description
The GS880Z18/36T is an 8Mbit Synchronous Static SRAM. GSIs NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles.

FEATUREs
• 512K x 18 and 256K x 36 configurations
• User configurable Pipeline and Flow Through mode
• NBT (No Bus Turn Around) functionality allows zero wait read-write-read bus utilization
• Fully pin compatible with both pipelined and flow through NtRAM™, NoBL™ and ZBT™ SRAMs
• Pin compatible with 2M, 4M and 16M (future) devices
• 3.3 V +10%/–5% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleave Burst mode
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• Clock Control, registered address, data, and control
• ZZ Pin for automatic power-down
• JEDEC-standard 100-lead TQFP package