Description
This device contains 8 master-slave flip-flops with a common clock and common clear. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the clock input. The clear input when low, sets all outputs to a low state.

Features
•  High Speed Operation: tpd(Clock to Q) = 18 ns typ (CL= 50 pF)
•  High Output Current: Fanout of 10 LSTTL Loads
•  Wide Operating Voltage: VCC= 2 to 6 V
•  Low Input Current: 1 µA max
•  Low Quiescent Supply Current: ICC(static) = 4 µA max (Ta = 25°C)