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ICS9148-11 数据手册 ( 数据表 ) - Integrated Circuit Systems

ICS9148-11 image

零件编号
ICS9148-11

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14 Pages

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448.8 kB

生产厂家
ICST
Integrated Circuit Systems ICST

General Description
TheICS9148-11 generates all clocks required for high speed RISC or CISC microprocessor systems such as Intel PentiumPro. An output enable pin is provided for testability. MODE allows power management functions: CPU_STOP#, PCI_STOP# & PWR_DWN#.
High drive BCLK outputs typically provide greater than 1V/ns slew rate into 30pF loads. PCLK outputs typically provide better than 1V/ ns slew rate into 20pF loads while maintaining50–5% duty cycle. The REF clock outputs typically provide better than 0.5V/ns slew rates.


FEATUREs
 • Generates four processor, six bus, one 14.31818MHz and 12 SDRAM clocks.
 • Synchronous clocks skew matched to 250ps window on CPU, SDRAM and 500ps window on BUS clocks.
 • CPUCLKs to BUS clocks skew 1-4 ns (CPU early)
 • Test clock mode eases system design
 • Custom configurations available
 • VDD(1:3) - 3.3V –10% (inputs 5V tolerant w/series R )
 • VDDL(1:2) - 2.5V or 3.3V –5%
 • PC serial configuration interface
 • Power Management Control Input pins
 • 48-pin SSOP package

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