DESCRIPTION:
IS43/46R83200B is a 4-bank x 8,388,608-word x8bit, IS43/46R16160B is a 4-bank x 4,194,304-word x 16bit double data rate synchronous DRAM , with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK. Input data is registered on both edges of data strobe, and output data and data strobe are referenced on both edges of CLK. The device achieves very high speed clock rate up to 200 MHz.

FEATURES:
• Vdd =Vddq = 2.5V+0.2V (-5, -6, -75)
• Double data rate architecture; two data transfers
   per clock cycle.
• Bidirectional , data strobe (DQS) is transmitted/
   received with data
• Differential clock input (CLK and /CLK)
• DLL aligns DQ and DQS transitions with CLK
   transitions edges of DQS
• Commands entered on each positive CLK edge;
• Data and data mask referenced to both edges of
   DQS
• 4 bank operation controlled by BA0 , BA1
   (Bank Address)
• /CAS latency -2.0 / 2.5 / 3.0 (programmable) ;
   Burst length -2 / 4 / 8 (programmable)
   Burst type -Sequential / Interleave (programmable)
• Auto precharge/ All bank precharge controlled
   by A10
• 8192 refresh cycles / 64ms (4 banks concurrent
   refresh)
• Auto refresh and Self refresh
• Row address A0-12 / Column address A0-9(x8)/
   A0-8(x16)
• SSTL_2 Interface
• Package:
   66-pin TSOP II (x8 and x16)
   60-ball TF-BGA (x16 only)
• Temperature Range:
   Commercial (0°C to +70°C)
   Industrial (-40°C to +85°C)
   Automotive (-40°C to +85°C)