Description
The ispLSI 1032E is a High Density Programmable Logic Device containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 1032E device offers 5V non-volatile in-system programmability of the logic, as well as the interconnects to provide truly reconfigurable systems. A functional superset of the ispLSI 1032 architecture, the ispLSI 1032E device adds two new global output enable pins.

FEATUREs
• HIGH DENSITY PROGRAMMABLE LOGIC
    — 6000 PLD Gates
    — 64 I/O Pins, Eight Dedicated Inputs
    — 192 Registers
    — High Speed Global Interconnect
    — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.
    — Small Logic Block Size for Random Logic
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
    — fmax = 125 MHz Maximum Operating Frequency
    — tpd = 7.5 ns Propagation Delay
    — TTL Compatible Inputs and Outputs
    — Electrically Erasable and Reprogrammable
    — Non-Volatile
    — 100% Tested at Time of Manufacture
    — Unused Product Term Shutdown Saves Power
• IN-SYSTEM PROGRAMMABLE
    — In-System Programmable (ISP™) 5V Only
    — Increased Manufacturing Yields, Reduced Time-to-Market and Improved Product Quality
    — Reprogram Soldered Devices for Faster Prototyping
• OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS
    — Complete Programmable Device Can Combine Glue Logic and Structured Designs
    — Enhanced Pin Locking Capability
    — Four Dedicated Clock Input Pins
    — Synchronous and Asynchronous Clocks
    — Programmable Output Slew Rate Control to Minimize Switching Noise
    — Flexible Pin Placement
    — Optimized Global Routing Pool Provides Global Interconnectivity
    — Lead-Free Package Options