The MC100LVEL38 is a low skew ÷2, ÷4/6 clock generation chip designed explicitly for low skew clock generation applications. The MC100EL38 is pin and functionally equivalent to the MC100LVEL38 but is specified for operation at the standard 100K ECL voltage supply. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differential or single-ended LVECL or, if positive power supplies are used, LVPECL input signal. In addition, by using the VBB output, a sinusoidal source can be AC coupled into the device (see Interfacing section of the ECLinPS Data Book DL140/D). If a single-ended input is to be used, the VBB output should be connected to the CLK input and bypassed to ground via a 0.01µF capacitor. The VBB output is designed to act as the switching reference for the input of the LVEL38 under single-ended input conditions, as a result, this pin can only source/sink up to 0.5mA of current.

• 50ps Output-to-Output Skew
• Synchronous Enable/Disable
• Master Reset for Synchronization
• 75kΩ Internal Input Pulldown Resistors
• >1500V ESD Protection
• Low Voltage VEE Range of –3.0 to –3.8V