The MC10161 is designed to decode a three bit input word to a one of eight line output. The selected output will be low while all other outputs will be high. The enable inputs, when either or both are high, force all outputs high.
The MC10161 is a true parallel decoder. No series gating is used internally, eliminating unequal delay times found in other decoders. This design provides the identical 4 ns delay from any address or enable input to any output.
   
• PD = 315 mW typ/pkg (No Load)
• tpd = 4.0 ns typ
• tr, tf = 2.0 ns typ (20%–80%)