Bus transceiver, inverting (3-State)

DESCRIPTION
The 74F862 bus transceiver provides a high performance inverting bus interface for wide data/address paths of buses carrying parity.
   
FEATURES
• Provide high performance bus interface buffering for wide
    data/address paths or buses carrying parity
• High impedance NPN base inputs for reduced loading (20 µA in
    HIGH and LOW states)
• IIL is 20 µA for minimum bus loading
• Buffered control inputs for light loading, or increased fan-in as
    required with MOS microprocessors
• Positive and negative over-shoots are clamped to ground
• 3-State outputs glitch free during power-up and power-down
• Slim dual In-line (DIP) 300 mil package
• Broadside pinout
• Outputs sink 64 mA