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P87C51MB2 数据手册 ( 数据表 ) - NXP Semiconductors.

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零件编号
P87C51MB2

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34 Pages

File Size
391.1 kB

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NXP
NXP Semiconductors. NXP

GENERAL DESCRIPTION
The P87C51Mx2 represents the first microcontroller based on Philips Semiconductors’ new 51MX core. The P87C51MC2 features 96 Kbytes of OTP program memory and 3 Kbytes of data SRAM, while the P87C51MB2 has 64 Kbytes of OTP and 2 Kbytes of RAM. In addition, both devices are equipped with a Programmable Counter Array (PCA), a watchdog timer that can be configured to different time ranges through SFR bits, as well as two enhanced UARTs or one enhanced UART and an SPI.


KEY FEATURES
• Extended features of the 51MX Core:
   - 23-bit program memory space and 23-bit data memory space - linear program and data address range expanded to support up to 8 Mbytes each
   - Program counter expanded to 23 bits
   - Stack pointer extended to 16 bits enabling stack space beyond the 80C51 limitation
   - New 23-bit extended data pointer and two 24-bit universal pointers greatly improve C compiler code efficiency in using pointers to access variables in different spaces.
• 100% binary compatibility with the classic 80C51 so that existing code is completely reusable
• Up to 24 MHz CPU clock with 6 clock cycles per machine cycle
• 96 Kbytes or 64 Kbytes of on-chip OTP
• 3 Kbytes or 2 Kbytes of on-chip RAM
• Programmable Counter Array (PCA)
• Two full-duplex enhanced UARTs
• Industry-standard Serial Peripheral Interface (SPI)

KEY BENEFITS
• Increases program/data address range to 8 Mbytes each
• Enhances performance and efficiency for C programs
• Fully 80C51-compatible microcontroller
• Provides seamless and compelling upgrade path from classic 80C51
• Preserves 80C51 code base, investment/knowledge, and peripherals & ASICs
• Supported by 80C51 development and programming tools (Keil, Nohau, BP Micro, etc.)
• The P87C51Mx2 makes it possible to develop applications at a lower cost and with a reduced time-to-market


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