GENERAL DESCRIPTION
This document gives preliminary information about the TDA8044 and TDA8044A, which are the successors of the TDA8043. The TDA8044A is only specified where the product deviates from the TDA8044, all other references are the same. The TDA8044 is backwards compatible with the TDA8043, with respect to pinning and the I2C-bus software.

FEATURES
• General features:
    – One-chip Digital Video Broadcasting (DVB) compliant Quadrature Phase Shift Keying (QPSK) and Binary Phase Shift Keying (BPSK) demodulator and concatenated Viterbi/Reed-Solomon decoder with de-interleaver and de-randomizer (ETS 300 421)
    – 3.3 V supply voltage (input pads are 5 V tolerant)
    – Standby mode for low power dissipation
    – Internal clock PLL to allow low frequency crystal application and selectable clock frequencies
    – Power-on reset module
    – Package: QFP100
    – Boundary scan test.
• QPSK/BPSK demodulator:
    – Interpolator and anti-alias filter to handle a large range of symbol rates without additional external filtering
    – On-chip AGC of the analog input I and Q baseband signals or tuner AGC control
    – Two on-chip matched Analog-to-Digital Converters (ADCs; 7 bits)
    – Half Nyquist (square root raised-cosine) filter with selectable roll-off factor
    – Large range of symbol frequencies: 0.5 to 45 Msymbols/s for TDA8044 and 0.5 to 30 Msymbols/s for TDA8044A, including Single Carrier Per Channel (SCPC) function
    – Can be used at low channel Signal-to-Noise ratio (S/N)
    – Internal carrier recovery, clock recovery and AGC loops with programmable loop filters
    – Two loop carrier recovery enabling phase tracking of the incoming symbols
    – Software carrier sweep for low symbol rate applications
    – Signal-to-noise ratio estimation
    – External indication of demodulator lock.
    – Truncation length: 144
    – Automatic synchronization
    – Channel Bit Error Rate (BER) estimation
    – External indication of Viterbi sync lock
    – Differential decoding optional.
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