GENERAL DESCRIPTION
The 128MByte (1Gb) DDR SDRAM is a high-speed CMOS, dynamic random-access, memory using 5 chips containing 268,435,456 bits. Each chip is internally configured as a quad-bank DRAM. Each of the chip’s 67,108,864-bit banks is organized as 8,192 rows by 512 columns by 16 bits.

FEATURES
■ High Frequency = 200, 250, 266MHz
■ Package:
   • 219 Plastic Ball Grid Array (PBGA), 32 x 25mm
■ 2.5V ±0.2V core power supply
■ 2.5V I/O (SSTL_2 compatible)
■ Differential clock inputs (CLK and CLK)
■ Commands entered on each positive CLK edge
■ Internal pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle
■ Programmable Burst length: 2,4 or 8
■ Bidirectional data strobe (DQS) transmitted/received with data, i.e., source-synchronous data capture (one per byte)
■ DQS edge-aligned with data for READs; center-aligned with data for WRITEs
■ DLL to align DQ and DQS transitions with CLK
■ Four internal banks for concurrent operation
■ Two data mask (DM) pins for masking write data
■ Programmable IOL/IOH option
■ Auto precharge option
■ Auto Refresh and Self Refresh Modes
■ Commercial, Industrial and Military Temperature Ranges
■ Organized as 16M x 72
■ Weight: WEDPND16M72S-XBX - 2.5 grams typical

BenefitS
■ 40% SPACE SAVINGS
■ Reduced part count
■ Reduced I/O count
   • 34% I/O Reduction
■ Reduced trace lengths for lower parasitic capacitance
■ Suitable for hi-reliability applications
■ Laminate interposer for optimum TCE match
■ Upgradeable to 32M x 72 density (contact factory for information)