HS-80C86RH(1995) 查看數據表（PDF） - Intersil
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HS-80C86RH Datasheet PDF : 37 Pages
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HS-80C86RH
The instruction stream queuing mechanism allows the BlU to
keep the memory utilized very efficiently. Whenever there is
space for at least 2 bytes in the queue, the BlU will attempt a
word fetch memory cycle. This greatly reduces “dead-time”
on the memory bus. The queue acts as a First-In-First-Out
(FlFO) buffer, from which the EU extracts instruction bytes
as required. If the queue is empty (following a branch
instruction, for example), the first byte into the queue
immediately becomes available to the EU.
The execution unit receives pre-fetched instructions from the
BlU queue and provides un-relocated operand addresses to
the BlU. Memory operands are passed through the BlU for
processing by the EU, which passes results to the BlU for
storage.
Memory Organization
The processor provides a 20-bit address to memory, which
locates the byte being referenced. The memory is organized
as a linear array of up to 1 million bytes, addressed as
00000(H) to FFFFF(H). The memory is logically divided into
code, data, extra and stack segments of up to 64K bytes
each, with each segment falling on 16 byte boundaries. (See
Figure 1).
FFFFFH
64K BIT
SEGMENT
REGISTER FILE
CS
SS
DS
ES
+ OFFSET
CODE SEGMENT
XXXXOH
STACK SEGMENT
DATA SEGMENT
EXTRA SEGMENT
00000H
FIGURE 1. HS-80C86RH MEMORY ORGANIZATION
TABLE 7.
DEFAULT
TYPE OF MEMORY SEGMENT
REFERENCE
BASE
ALTERNATE
SEGMENT
BASE
Instruction Fetch
CS
None
Stack Operation
SS
None
Variable
DS
CS, ES, SS
(Except Following)
String Source
DS
CS, ES, SS
String Destination
ES
None
BP Used as Base
Register
SS
CS, DS, ES
OFFSET
IP
SP
Effective
Address
SI
DI
Effective
Address
All memory references are made relative to base addresses
contained in high speed segment registers. The segment
types were chosen based on the addressing needs of
programs. The segment register to be selected is
automatically chosen according to the specific rules of
Table 7. All information in one segment type share the same
logical attributes (e.g. code or data). By structuring memory
into relocatable areas of similar characteristics and by
automatically selecting segment registers, programs are
shorter, faster and more structured. (See Table 7).
Word (16-bit) operands can be located on even or odd
address boundaries and are thus not constrained to even
boundaries as is the case in many 16-bit computers. For
address and data operands, the least significant byte of the
word is stored in the lower valued address location and the
most significant byte in the next higher address location. The
BlU automatically performs the proper number of memory
accesses, one if the word operand is on an even byte
boundary and two if it is on an odd byte boundary. Except for
the performance penalty, this double access is transparent to
the software. The performance penalty does not occur for
instruction fetches; only word operands.
Physically, the memory is organized as a high bank (D15-
D6) and a low bank (D7-D0) of 512K bytes addressed in par-
allel by the processor’s address lines.
Byte data with even addresses is transferred on the D7-D0
bus lines while odd addressed byte data (A0 HIGH) is
transferred on the D15-D6 bus lines. The processor provides
two enable signals, BHE and A0, to selectively allow reading
from or writing into either an odd byte location, even byte
location, or both. The instruction stream is fetched from
memory as words and is addressed internally by the
processor at the byte level as necessary.
In referencing word data, the BlU requires one or two
memory cycles depending on whether the starting byte of
the word is on an even or odd address, respectively. Con-
sequently, in referencing word operands performance can be
optimized by locating data on even address boundaries. This
is an especially useful technique for using the stack, since
odd address references to the stack may adversely affect the
context switching time for interrupt processing or task multi-
plexing.
Certain locations in memory are reserved for specific CPU
operations (See Figure 2). Locations from address FFFF0H
through FFFFFH are reserved for operations including a
jump to the initial program loading routine. Following RESET,
the CPU will always begin execution at location FFFF0H
where the jump must be located. Locations 00000H through
003FFH are reserved for interrupt operations. Each of the
256 possible interrupt service routines is accessed through
its own pair of 16-bit pointers - segment address pointer and
offset address pointer. The first pointer, used as the offset
address, is loaded into the 1P and the second pointer, which
designates the base address is loaded into the CS. At this
point program control is transferred to the interrupt routine.
The pointer elements are assumed to have been stored at
the respective places in reserved memory prior to occur-
rence of interrupts.
Spec Number 518055
868
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