FS6261-01 查看數據表（PDF） - AMI Semiconductor
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FS6261-01 Datasheet PDF : 17 Pages
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January 2000
Table 9: AC Timing Specifications, continued
Unless otherwise stated, all power supplies = 3.3V, no load on any output, and ambient temperature TA = 25°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and
are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical. Spread spectrum modulation is disabled except for Rise/Fall time measurements.
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
133MHz
MIN. TYP. MAX.
100MHz
MIN. TYP. MAX.
UNITS
PCI_1:7, PCI_F Clock Outputs (3.3V Type 5 Clock Buffer)
Duty Cycle *
dt
Ratio of high pulse width to one
clock period, measured at 1.5V
45
47
55
45
50
55
%
Clock Skew *
PCI_F to PCI @ 1.5V, CL=30pF
tskw
PCI to PCI @ 1.5V, CL=30pF
+660
+60
+660
ps
+60
Jitter, Long Term (σy(τ)) *
On rising edges 500µs apart at 1.5V
tj(LT)
relative to an ideal clock, CL=30pF,
220
all PLLs active
131
ps
Jitter, Period (peak-peak) *
tj(∆P)
From rising edge to rising edge at
1.5V, CL=30pF, all PLLs active
76
95
ps
Rise Time *
tr min
Measured @ 0.4V – 2.4V; CL=10pF
1.2
tr max
Measured @ 0.4V – 2.4V; CL=30pF
1.8
1.3
ns
1.8
Fall Time *
tf min
Measured @ 2.4V – 0.4V; CL=10pF
1.3
tf max
Measured @ 2.4V – 0.4V; CL=30pF
1.6
1.2
ns
1.5
Enable Delay *
tDLH
via PCI_STOP#
1.0
8.0 1.0
8.0
ns
Disable Delay *
tDHL
via PCI_STOP#
1.0
8.0 1.0
8.0
ns
CK66_0:3 Clock Outputs (3.3V Type 5 Clock Buffer)
Duty Cycle *
Clock Skew *
Jitter, Long Term (σy(τ)) *
Jitter, Period (peak-peak) *
Rise Time *
Fall Time *
Enable Delay *
Disable Delay *
dt
Ratio of high pulse width to one
clock period, measured at 1.5V
45
52
55
45
51
55
%
tskw
CK66 to CK66 @ 1.5V, CL=30pF
120
120
ps
On rising edges 500µs apart at 1.5V
tj(LT)
relative to an ideal clock, CL=30pF,
137
all PLLs on
123
ps
tj(∆P)
From rising edge to rising edge at
1.5V, CL=30pF, all PLLs active
75
79
ps
tr min
Measured @ 0.4V – 2.4V; CL=10pF
0.9
tr max
Measured @ 0.4V – 2.4V; CL=30pF
1.5
0.9
ns
1.5
tf min
Measured @ 2.4V – 0.4V; CL=10pF
1.0
tf max
Measured @ 2.4V – 0.4V; CL=30pF
1.4
1.0
ns
1.4
tDLH
via CPU_STOP#
1.0
8.0 1.0
8.0
ns
tDHL
via CPU_STOP#
1.0
8.0 1.0
8.0
ns
Figure 9: Clock Skew Diagrams
,62
CPU 1.25V
2.5V
tskw
CK66
1.5V
3.3V
CPU 1.25V
2.5V
tskw
1.25V
APIC
2.5V
CK66 1.5V
3.3V
tskw
PCI 1.5V
3.3V
2.5V to 3.3V Clock Offset
2.5V to 2.5V Clock Skew
3.3V to 3.3V Clock Skew
13
1.31.00
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