5962F9563501QYC 查看數據表（PDF） - Intersil

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5962F9563501QYC

Radiation Hardened Real Time Express™ Microcontroller

Intersil 

HS-RTX2010RH

Timing Diagrams (Continued)

PCLK

NMI

e1

t44

INTA

MA

e2

e4

e5

t67

t68

t26

t28

NMI

VECTOR

NOTES:

14. Events in an interrupt sequence are as follows:

e1. The Interrupt Controller samples the interrupt request inputs on the rising edge of PCLK. If NMI rises between e1 and the rising edge of

PCLK prior to e5, the interrupt vector will be for NMI.

e2. If any interrupt requests were sampled, the Interrupt Controller issues an interrupt request to the core on the falling edge of PCLK.

e4. When the core samples an interrupt request on the falling edge of PCLK, an Interrupt Acknowledge cycle will begin on the next rising edge

of PCLK.

e5. Following the detection of an interrupt request by the core, an Interrupt Acknowledge cycle begins. The interrupt vector will be based on the

highest priority interrupt request active at this time.

15. t44 is only required to determine when the Interrupt Acknowledge cycle will occur.

16. Interrupt requests should be held active until the Interrupt Acknowledge cycle for that interrupt occurs.

17. NMI has a glitch filter which requires the signal that initiates NMI last at least two rising and two falling edges of ICLK.

FIGURE 8. NON-MASKABLE INTERRUPT TIMING

HS-RTX2010RH Microcontroller

The HS-RTX2010RH is designed around the RTX Processor

core, which is part of the Intersil Standard Cell Library.

This processor core has eight 16-bit internal registers, an

ALU, internal data buses, and control hardware to perform

instruction decoding and sequencing.

On-chip peripherals which the HS-RTX2010RH includes are

Memory Page Controller, an Interrupt Controller, three

Timer/Counters, and two Stack Controllers. Also included

are a Multiplier-Accumulator (MAC), a Barrel Shifter, and a

Leading Zero Detector for floating point support.

Off-chip user interfaces provide address and data access to

Main Memory and ASIC I/O devices, user defined interrupt

signals, and Clock/Reset controls.

Figure 9 shows the data paths between the core, on-chip

peripherals, and off-chip interfaces.

The HS-RTX2010RH microcontroller is based on a two-stack

architecture. These two stacks, which are Last-In-First-Out

(LIFO) memories, are called the Parameter Stack and the

Return Stack.

Two internal registers, TOP and NEXT , provide the top

two elements of the 16-bit wide Parameter Stack, while the

remaining elements are contained in on-chip memory (“stack

memory”).

The top element of the Return Stack is 21 bits wide, and is

stored in registers I and IPR , while the remaining

elements are contained in stack memory.

The highly parallel architecture of the RTX is optimized for

minimal Subroutine Call/Return overhead. As a result, a

Subroutine Call takes one Cycle, while a Subroutine Return

is usually incorporated into the preceding instruction and

does not add any processor cycles. This parallelism

provides for peak execution rates during simultaneous bus

operations which can reach the equivalent of 32 million

Forth language operations per second at a clock rate of

8MHz. Typical execution rates exceed 8 million operations

per second.

Intersil factory applications support for this device is limited.

RTS-C C-Compiler support is provided by Highland Software

at highlandsoft@compuserve.com. Development system

tools are supported by Micro Processor Engineering Limited

(UK) at 441 703 631441. A HS-RTX2010RH programmers

reference manual can be obtained through your local Intersil

Sales Office.

9

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