GS82032 查看數據表（PDF） - Giga Semiconductor

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GS82032

64K x 32 2M Synchronous Burst SRAM

Giga Semiconductor 

GS82032AT/Q-180/166/133/100

Flow Through Read-Write Cycle Timing

Single Read

Single Write

Burst Read

CK

ADSP

tS tH

tKC

tKH tKL

ADSP is blocked by E inactive

tS tH ADSC initiated read

ADSC

tS tH

ADV

A0–An

GW

tS tH

RD1

tS tH

tS

WR1

RD2

tH

BW

BA–BD

E1

E2

E3

tS tH

tS tH

WR1

E1 masks ADSP

tS tH

E2 and E3 only sampled with ADSP and ADSC

tS tH

Deselected with E3

tOE tOHZ

G

DQA–DQD

tKQ

Hi-Z

Q1A

tS tH

D1A

Q2A

Q2B

Q2C Q2D Q2A

Burst wrap around to it’s initial state

Rev: 1.09 7/2002

16/23

© 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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