GS82032 查看數據表（PDF） - Giga Semiconductor

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GS82032

64K x 32 2M Synchronous Burst SRAM

Giga Semiconductor 

GS82032AT/Q-180/166/133/100

Pipelined SCD Read - Write Cycle Timing

CK

ADSP

ADSC

ADV

A0–An

GW

BW

BA–BWD

E1

E2

E3

G

DQA–DQD

Single Read

Single Write

tKL

Burst Read

tS tH

tKH

tKC

ADSP is blocked by E inactive

tS tH ADSC initiated read

tS tH

tS tH

RD1

tS tH

WR1

RD2

tS

tH

tS tH

tS tH

tS tH

tS tH

WR1

E1 masks ADSP

E2 and E3 only sampled with ADSP and ADSC

Deselected with E3

tOE tOHZ

tS tH

tKQ

Hi-Z

Q1A

D1A

Q2A

Q2B

Q2C Q2D

Rev: 1.09 7/2002

18/23

© 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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