MAX100 查看數據表（PDF） - Maxim Integrated
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MAX100 Datasheet PDF : 16 Pages
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250Msps, 8-Bit ADC with Track/Hold
TIMING CHARACTERISTICS
(VEE = -5.2V, VCC = +5V, RL = 50Ω to -2V, VART = 1.02V, VARB = -1.02V, TA = +25°C, unless otherwise noted.)
PARAMETER
Clock Pulse Width Low
Clock Pulse Width High
CLK to DCLK
Propagation Delay
DCLK to A/BData
Propagation Delay
Rise Time
Fall Time
Pipeline Delay
(Latency)
SYMBOL
tPWL
tPWH
tPD1
tPD2
tR
tF
CONDITIONS
CLK, CLK, Figures 1 and 2
CLK, CLK, Figures 1 and 2
DIV = 0, Figure 1
DIV = 1, Figure 2
DIV = 0, Figure 1
DIV = 1, Figure 2
20% to 80%
DCLK
DATA
20% to 80%
DCLK
DATA
tNPD
See Figures 3 and 4
and Table 1 (delay
depends on output
mode)
Divide-by-1 mode
Divide-by- AData
2 mode BData
MIN TYP
1.9
1.9
0.8
1.9
0.5
-1.4
500
700
600
550
7 1/2
7 1/2
8 1/2
MAX
5.0
2.4
5.7
2.2
-0.1
UNITS
ns
ns
ns
ns
ps
ps
7 1/2
7 1/2
8 1/2
Clock
Cycles
Note 3: All devices are 100% production tested at +25°C and are guaranteed by design for TA = TMIN to TMAX as specified.
Note 4: Deviation from best-fit straight line. See Integral Nonlinearity section.
Note 5: See the Signal-to-Noise Ratio and Effective Bits section in the Definitions of Specifications.
Note 6: SNR calculated from effective bits performance using the following equation: SNR (dB) = 1.76 + (6.02) (effective bits).
Note 7: Clock pulse width minimum requirements tPWL and tPWH must be observed to achieve stated performance.
Note 8: Functionality guaranteed for -1.07 ≤ VIH ≤ -0.7 and -2.0 ≤ VIL ≤ -1.5.
Note 9: Outputs terminated through 50Ω to -2.0V.
__________________________________________Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
INTEGRAL NONLINEARITY
vs. OUTPUT CODE
0.75
0.50
0.25
0
-0.25
-0.50
-0.75
0
64
128
192
256
OUTPUT CODE
0.75
0.50
0.25
0
-0.25
-0.50
-0.75
0
DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
64
128
192
256
OUTPUT CODE
4 _______________________________________________________________________________________
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