MAX100 查看數據表（PDF） - Maxim Integrated

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产品描述 (功能)

比赛名单

MAX100

250Msps, 8-Bit ADC with Track/Hold

Maxim Integrated 

250Msps, 8-Bit ADC with Track/Hold

CLK

CLK

DCLK

DCLK

AData

BData

tpd1

tpd2

tpwl

tpwh

Figure 2. Output Timing: Divide-by-2 or Divide-by-5 Mode (DIV = 1)

N-1

N N+1

CLK

DCLK

1

2

3

4

5

6

7

8

AData

N-1

N N+1

BData

tpd1

N-1

tpd2

tNPD

Figure 3. Output Timing: Clock to Data, Divide-by-1 Mode (fast mode, DIV = 0)

N N+1

N-2 N-1

N N+1 N+2

CLK

DCLK

1

2

3

4

5

AData

N-1

N+1

N+3

BData

tpd2

tNPD

Figure 4. Output Timing: Divide-by-2 Mode (DIV = 1)

N-2

N

N+2

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