MAX100 查看數據表（PDF） - Maxim Integrated
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MAX100 Datasheet PDF : 16 Pages
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250Msps, 8-Bit ADC with Track/Hold
______________________________________________________________Pin Description
PIN
NAME
1
PAD
Internal connection, leave open.
FUNCTION
2, 62
3, 61
CLK
Complementary Differential Clock Inputs. Can be driven from standard 10K ECL with the following
considerations: Internally, pins 2 & 62 and 3 & 61 are the ends of a 50Ω transmission line. Either end
CLK
can be driven, with the other end terminated with 50Ω to -2V. See Typical Operating Circuit.
4, 7, 15, 49,
57, 60, 64,
67, 70, 71,
74, 77, 78,
79, 82, 84
GND
5, 6, 9, 10,
31, 33, 35,
48, 58, 59,
63, 81, 83
N.C.
8, 21, 43, 56
11
12
13
14
16
17, 20, 23,
26, 36, 39,
42, 45
19, 22, 25,
28, 38, 41,
44, 47
VCC
DIV
MOD
DCLK
DCLK
A=B
A7–A0
B7–B0
18, 24, 27,
30, 34, 37,
40, 46
DGND
29
32, 69, 80
50
51
SUB
VEE
VART
VARTS
Power-Supply Ground. Connect GND and DGND pins (Note 10).
No Connect—there is no internal connection to these pins.
Positive power supply, +5V ±5% nominal
Divide Enable Input. DIV and MOD select the output modes. See Table 1.
Modulus. MOD and DIV select the output modes. See Table 1.
Complementary Differential Clock Outputs. Used to synchronize following circuitry: AData and BData
outputs are valid tPD2 after the rising edge of DCLK. See Figures 1–4.
Sets AData equal to BData when asserted (A=B = 1). See Table 1.
AData and BData Outputs. A0 and B0 are the LSBs, and A7 and B7 are the MSBs. AData and BData
outputs conform to standard 10K ECL logic swings and drive 50Ω transmission lines. Terminate with
50Ω to -2V. See Figures 1–4.
Power-Supply Ground. Connect all ground (GND, DGND) pins together, as described in Note 10.
Circuit Substrate Contact. This pin must be connected to VEE.
Negative Power Supply, -5.2V ±5% nominal
Positive Reference Voltage Input (Note 11)
Positive Reference Voltage Sense (Note 11)
_______________________________________________________________________________________ 7
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