MSM80C86A-10GS 查看數據表（PDF） - Oki Electric Industry

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MSM80C86A-10GS

16-Bit CMOS MICROPROCESSOR

Oki Electric Industry 

¡ Semiconductor

MSM80C86A-10RS/GS/JS

Asynchronous Signal Recognition

CLK

NMI

INTR Signal

TEST

tINVCH (See NOTE 1)

NOTE: 1 Setup requirements for asynchronous

signals only to guarantee recognition

at next CLK

Bus Lock Signal Timing (Maximum Mode Only)

CLK

LOCK

Any CLK Cycle

Any CLK Cycle

tCLAV

tCLAV

Reset Timing

VCC

CLK

Reset

≥ 50msec

tDVCLtCLDX

≥ 4 CLK Cycles

Request/Grant Sequence Timing (Maximum Mode Only)

Any CLK Cycle

> 0 CLK Cycle

CLK

tCLGH

RQ/GT

AD15 - AD0

A19/S6 - A16/S3

S2, S1, S0,

RD, CLOCK

BHE/S7

≥ tCLCL

tGVCH

tCHGX

Pulse 1

Coprocessor

RQ

MSM80C86A-10

tCLGL

Pulse 2

80C86AGT

≥ tCLCL

tCLGH

Pulse 3

Coprocessor

Release

tCLAZ

Coprocessor

(See NOTE 1)

MSM80C86A-10

NOTE: 1 The coprocessor may not drive the buses outside the region shown without risking contention.

Hold/Hold Acknowledge Timing (Minimum Mode Only)

CLK

HOLD

HLDA

AD15 - AD0,

A19/S6 - A16/S3,

RD,

BHE/S7, M/IO

DT/R, WR, DEN

≥ 1 CLK Cycle

1 or 2 Cycles

tHVCH

MSM80C86A-10

tHVCH

tCLHAV

tCLAZ

Coprocessor

tCLHAV

MSM80C86A-10

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