MSM80C86A-10GS 查看數據表（PDF） - Oki Electric Industry

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MSM80C86A-10GS

16-Bit CMOS MICROPROCESSOR

Oki Electric Industry 

¡ Semiconductor

MSM80C86A-10RS/GS/JS

INTA

INTERRUPT ACKNOWLEDGE: Output

This line is a read strobe signal for the interrupt acknowledge cycle. This line is active low.

TEST

TEST: Input

This line is examined by the WAIT instruction.

When TEST is high, the CPU enters idle cycle.

When TEST is low, the CPU exits the idle cycle.

NMI

NON MASKABLE INTERRUPT: Input

This line causes a type 2 interrupt.

NMI is not maskable.

This signal is internally synchronized and needs 2-clock cycles of pulse width.

RESET

RESET:Input

This signal causes the CPU to initialize immediately.

This signal is active high and must be at least four clock cycles.

CLK

CLOCK: Input

This signal provides the basic timing for the internal circuit.

MN/MX

MINIMUM/MAXIMUM: Input

This signal selects the CPU’s operating mode.

When VCC is connected, the CPU operates in Minimum mode.

When GND is connected, the CPU operates in Maximum mode.

VCC

VCC: +5V supplied.

GND

GROUND

The following pin function descriptions are maximum mode only. Other pin functions are

already described.

SO, S1, S2

STATUS: Output

These lines indicate bus status and they are used by the MSM82C88-2 Bus Controller to

generate all memory and I/O access control signals.

These lines are high impedance during hold acknowledge. These status lines are encoded as

shown.

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