RMLV0408E 查看數據表（PDF） - Renesas Electronics

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RMLV0408E

4Mb Advanced LPSRAM (512k word × 8bit)

Renesas Electronics 

RMLV0408E Series

Preliminary

Low VCC Data Retention Characteristics

Parameter

Symbol Min. Typ. Max. Unit

Test conditions*24

VCC for data retention

VDR

1.5

─

─

V

Vin ≥ 0V,

CS# ≥ VCC-0.2V

─

0.4*23

2

A ~+25°C

Data retention current

─

─

3

A ~+40°C

ICCDR

VCC=3.0V, Vin ≥ 0V,

CS# ≥ Vcc-0.2V

─

─

5

A ~+70°C

─

─

7

A ~+85°C

Chip deselect time to data retention

tCDR

Operation recovery time

tR

0

5

─

─

─

─

ns

ms

See retention waveform.

Note 23. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=25ºC), and not 100% tested.

24. CS# controls address buffer, WE# buffer, OE# buffer, and I/O buffer. If CS# controls data retention mode, Vin

levels (address, WE#, OE#, I/O) can be in the high-impedance state.

Low Vcc Data Retention Timing Waveforms (CS# controlled)

CS# Controlled

VCC

2.2V

tCDR

CS#

2.7V 2.7V

tR

VDR

CS# ≥ VCC - 0.2V

2.2V

R10DS0217EJ0001 Rev.0.01

2013.09.10

Page 10 of 10

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