AOZ1010 查看數據表（PDF） - Alpha and Omega Semiconductor

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AOZ1010

2A Simple Buck Regulator

Alpha and Omega Semiconductor 

AOZ1010

The zero given by the external compensation network,

capacitor CC (C5 in Figure 1), and resistor RC (R1 in

Figure 1), is located at:

fZ2

=

1

------------------------------------

2π × CC × RC

To design the compensation circuit, a target crossover

frequency fC for close loop must be selected. The system

crossover frequency is where control loop has unity gain.

The crossover frequency is also called the converter

bandwidth. Generally a higher bandwidth means faster

response to load transient. However, the bandwidth

should not be too high because of system stability

concerns. When designing the compensation loop,

converter stability under all line and load condition must

be considered.

Usually, it is recommended to set the bandwidth to be

less than 1/10 of switching frequency. The AOZ1010

operates at a fixed switching frequency range from

350kHz to 600kHz. The recommended crossover

frequency is less than 30kHz.

f C = 30kHz

The strategy for choosing RC and CC is to set the cross

over frequency with RC and set the compensator zero

with CC. Using selected crossover frequency, fC, to

calculate RC:

RC

=

f

C

×

--V-----O----

V FB

×

G-----2-E--π-A----×-×----C-G----O-C----S-

where;

fC is the desired crossover frequency,

VFB is 0.8V,

GEA is the error amplifier transconductance, which is 200 x 10-6

A/V, and

GCS is the current sense circuit transconductance, which is

5.64 A/V.

The compensation capacitor CC and resistor RC together

make a zero. This zero is put somewhere close to the

dominate pole, fP1, but lower than 1/5 of the selected

crossover frequency. CC can is selected by:

CC

=

1.5

-2---π-----×-----R-----C-----×-----f---P---1--

The previous equation can also be simplified to:

CC

=

C-----O------×-----R-----L-

RC

An easy-to-use application software which helps to

design and simulate the compensation loop can be found

at www.aosmd.com.

Table 3 lists the values for a typical output voltage design

when output is 44µF ceramics capacitor.

Table 3.

VOUT

1.8V

3.3V

5V

8V

L1

2.2µH

3.3µH

4.7µH

10µH

RC

20kΩ

31.6kΩ

49.9kΩ

80.6kΩ

CC

1.5nF

1.0nF

1.0nF

0.82nF

Thermal Management and Layout

Consideration

In the AOZ1010 buck regulator circuit, high pulsing cur-

rent flows through two circuit loops. The first loop starts

from the input capacitors, to the VIN pin, to the LX pins, to

the filter inductor, to the output capacitor and load, and

then returns to the input capacitor through ground.

Current flows in the first loop when the high side switch is

on. The second loop starts from the inductor, to the

output capacitors and load, to the PGND pin of the

AOZ1010, and to the LX pins of the AZO1010. Current

flows in the second loop when the low side diode is on.

In PCB layout, minimizing the two loops area reduces the

noise of this circuit and improves efficiency. A ground

plane is recommended to connect input capacitor, output

capacitor, and PGND pin of the AOZ1010.

In the AOZ1010 buck regulator circuit, the two major

power dissipating components are the AOZ1010 and

output inductor. The total power dissipation of converter

circuit can be measured by input power minus output

power.

P total _loss = V IN × I IN – V O × I O

The power dissipation of inductor can be approximately

calculated by output current and DCR of inductor.

P inductor _loss = IO2 × R inductor × 1.1

Rev. 1.0 November 2006

www.aosmd.com

Page 10 of 14

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