AOZ1010 查看數據表（PDF） - Alpha and Omega Semiconductor
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AOZ1010 Datasheet PDF : 14 Pages
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AOZ1010
Output Capacitor
The output capacitor is selected based on the DC output
voltage rating, output ripple voltage specification, and
ripple current rating.
The selected output capacitor must have a higher rated
voltage specification than the maximum desired output
voltage including ripple. De-rating needs to be con-
sidered for long term reliability.
Output ripple voltage specification is another important
factor for selecting the output capacitor. In a buck
converter circuit, output ripple voltage is determined by
inductor value, switching frequency, output capacitor
value and ESR. It can be calculated by the equation
below:
∆V O
=
∆I
L
×
ES
R
C
O
+
8-----×-----f---1-×-----C-----O--
where,
CO is output capacitor value, and
ESRCO is the equivalent series resistance of the output
capacitor.
When low ESR ceramic capacitor is used as output
capacitor, the impedance of the capacitor at the switching
frequency dominates. Output ripple is mainly caused by
capacitor value and inductor ripple current. The output
ripple voltage calculation can be simplified to:
∆V O
=
∆I
L
×
1
8-----×-----f----×-----C-----O--
If the impedance of ESR at switching frequency
dominates, the output ripple voltage is mainly decided
by capacitor ESR and inductor ripple current. The output
ripple voltage calculation can be further simplified to:
∆V O = ∆IL × ESRCO
For lower output ripple voltage across the entire operat-
ing temperature range, X5R or X7R dielectric type of
ceramic, or other low ESR tantalum capacitor or alumi-
num electrolytic capacitor may also be used as output
capacitors.
In a buck converter, output capacitor current is con-
tinuous. The RMS current of output capacitor is decided
by the peak to peak inductor ripple current. It can be
calculated by:
I CO_RMS = -∆----I---L--
12
Usually, the ripple current rating of the output capacitor
is a smaller issue because of the low current stress.
When the buck inductor is selected to be very small
and inductor ripple current is high, output capacitor could
be overstressed.
Loop Compensation
The AOZ1010 employs peak current mode control for
easy use and fast transient response. Peak current mode
control eliminates the double pole effect of the output
L&C filter. It greatly simplifies the compensation loop
design.
With peak current mode control, the buck power stage
can be simplified to be a one-pole and one-zero system
in frequency domain. The pole is dominant pole and can
be calculated by:
f P1
=
1
-2---π-----×-----C-----O-----×-----R-----L-
The zero is a ESR zero due to output capacitor and its
ESR. It is can be calculated by:
fZ1
=
1
-2---π-----×-----C-----O-----×-----E----S-----R-----C----O--
where;
CO is the output filter capacitor,
RL is load resistor value, and
ESRCO is the equivalent series resistance of output capacitor.
The compensation design is actually to shape the
converter close loop transfer function to get desired gain
and phase. Several different types of compensation
networks can be used for AOZ1010. For most cases, a
series capacitor and resistor network connected to the
COMP pin sets the pole-zero and is adequate for a stable
high-bandwidth control loop.
In the AOZ1010, FB pin and COMP pin are the inverting
input and the output of internal transconductance error
amplifier. A series R and C compensation network
connected to COMP provides one pole and one zero.
The pole is:
f P 2 = -2---π-----×-----C--G---C--E---×-A----G-----V---E----A--
where;
GEA is the error amplifier transconductance, which is 200 x 10-6
A/V,
GVEA is the error amplifier voltage gain, which is 500 V/V, and
CC is compensation capacitor.
Rev. 1.0 November 2006
www.aosmd.com
Page 9 of 14
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