MAX9268 查看數據表（PDF） - Maxim Integrated
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MAX9268 Datasheet PDF : 35 Pages
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Gigabit Multimedia Serial Link Deserializer
with LVDS System Interface
Pin Configuration
TOP VIEW
36 35 34 33 32 31 30 29 28 27 26 25
AGND
GND
IOVDD
ADD0
ADD1
LOCK
ERR
MS
SSEN
DRS
AVDD
AGND
37
38
39
40
41
42
43
44
45
46
47
48
+
MAX9268
EP
1 2 3 4 5 6 7 8 9 10 11 12
24 AGND
23 AVDD
22 GND
21 IOVDD
20 CNTL2/MCLK
19 CNTL1
18 SD/CNTL0
17 SCK
16 WS
15 PWDN
14 TX/SCL
13 RX/SDA
TQFP
PIN
1
2
3
4
5, 23, 32, 47
6, 7
8, 24, 31, 37, 48
9
NAME
BWS
INT
CDS
GPIO0
AVDD
IN+, IN-
AGND
EQS
Pin Description
FUNCTION
Bus-Width Select. Output width selection requires external pulldown or pullup resistor. Set
BWS = low for 3-channel mode. Set BWS = high for 4-channel mode.
Interrupt Input. Requires external pulldown or pullup resistor. A transition on the MAX9268’s
INT input toggles the GMSL serializer’s INT output.
Control Direction Selection. Control link direction selection input requires external pulldown or
pullup resistor. Set CDS = low for FC on the GMSL serializer side of the serial link. Set CDS =
high for FC on the MAX9268 side of the serial link.
General-Purpose I/O 0. Open-drain, general-purpose input/output with internal 60kI (typ)
pullup resistor to IOVDD. GPIO0 is high impedance during power-up and when PWDN = low.
3.3V Analog Power Supply. Bypass AVDD to AGND with 0.1FF and 0.001FF capacitors as
close as possible to the device with the smaller capacitor closest to AVDD.
Differential CML Input. Differential input of the serial link.
Analog Ground
Equalizer Select Input. EQS requires external pulldown or pullup resistor. The state of EQS
latches upon power-up or when resuming from power-down mode (PWDN = low). Set
EQS = low for 10.7dB equalizer boost (EQTUNE = 1001). Set EQS = high for 5.2dB
equalizer boost (EQTUNE = 0100).
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