MAX9268 查看數據表（PDF） - Maxim Integrated

零件编号

产品描述 (功能)

比赛名单

MAX9268

Gigabit Multimedia Serial Link Deserializer with LVDS System Interface

Maxim Integrated 

Gigabit Multimedia Serial Link Deserializer

with LVDS System Interface

Pin Description (continued)

PIN

10

11

12, 22, 38

13

14

15

16

17

18

19

20

21, 39

25, 26, 29, 30,

33–36

27, 28

40

41

42

43

NAME

GPIO1

DVDD

GND

RX/SDA

FUNCTION

General-Purpose I/O 1. Open-drain general-purpose input/output with internal 60kI (typ)

pullup resistor to IOVDD. GPIO1 is high impedance during power-up and when PWDN = low.

3.3V Digital Power Supply. Bypass DVDD to GND with 0.1FF and 0.001FF capacitors as close

as possible to the device with the smaller capacitor closest to DVDD.

Digital and I/O Ground

Receive/Serial Data. UART receive or I2C serial-data input/output with internal 30kI (typ)

pullup to IOVDD. In UART mode, RX/SDA is the Rx input of the MAX9268’s UART. In I2C

mode, RX/SDA is the SDA input/output of the MAX9268’s I2C master.

TX/SCL

PWDN

WS

SCK

SD/CNTL0

CNTL1

Transmit/Serial Clock. UART transmit or I2C serial-clock output with internal 30kI (typ) pullup

to IOVDD. In UART mode, TX/SCL is the Tx output of the MAX9268’s UART. In I2C mode, TX/

SCL is the SCL output of the MAX9268’s I2C master.

Power-Down. Active-low power-down input requires external pulldown or pullup resistor.

I2S Word-Select Output

I2S Serial-Clock Output

I2S Serial-Data/Control Output. Disable I2S to use SD/CNTL0 as an additional control output.

Control Output 1. CNTL1 is not active in 3-channel mode and remains low. To use CNTL1,

drive BWS high (4-channel mode) and set DISCNTL = 0. CNTL1 is mapped from DOUT27.

CNTL2/MCLK

Control 2/MCLK Output. CNTL2/MCLK is not active in 3-channel mode and remains low.

To use CNTL2/MCLK, drive BWS high (4-channel mode). CNTL2/MCLK is mapped from

DOUT28. CNTL/MCLK can also be used to output MCLK (see the Additional MCLK Output for

Audio Applications section).

IOVDD

I/O Supply Voltage. 1.8V to 3.3V logic I/O power supply. Bypass IOVDD to GND with

0.1FF and 0.001FF capacitors as close as possible to the device with the smaller

capacitor closest to IOVDD.

TXOUT_+, Differential LVDS Data Outputs. Set BWS = low (3-channel mode) to use TXOUT0_ to

TXOUT_- TXOUT2_. Set BWS = high (4-channel mode) to use TXOUT0_ to TXOUT3_.

TXCLKOUT+,

TXCLKOUT-

Differential LVDS Output for the LVDS Clock

ADD0

Address Selection Input 0. Three-level input to select the MAX9268’s device address

(see Table 2). The state of ADD0 latches upon power-up or when resuming from power-down

mode (PWDN = low).

ADD1

Address Selection Input 1. Three-level input to select the MAX9268’s device address

(see Table 2). The state of ADD1 latches upon power-up or when resuming from power-down

mode (PWDN = low).

LOCK

Open-Drain Lock Output with Internal 60kI (typ) Pullup to IOVDD. LOCK = high indicates

PLLs are locked with correct serial-word-boundary alignment. LOCK = low indicates PLLs are

not locked or incorrect serial-word-boundary alignment. LOCK remains low when the

configuration link is active. LOCK is high impedance when PWDN = low.

Active-Low, Open-Drain Video Data Error Output with Internal 60kI (typ) Pullup to IOVDD.

ERR

ERR goes low when the number of decoding errors during normal operation exceeds a pro-

grammed error threshold, or when at least one PRBS error is detected during PRBS test. ERR

is high impendence when PWDN = low.

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