5P49V5901BDDDNLGI 查看數據表（PDF） - Integrated Device Technology
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5P49V5901BDDDNLGI Datasheet PDF : 37 Pages
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5P49V5901 DATASHEET
Table 1: Pin Descriptions
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Name
CLKIN
CLKINB
XOUT
XIN/REF
VDDA
CLKSEL
SD/OE
SEL1/SDA
SEL0/SCL
VDDO4
OUT4
OUT4B
OUT3B
OUT3
VDDO3
OUT2B
OUT2
VDDO2
OUT1B
OUT1
VDDO1
Type
Input
Internal
Pull-down
Input
Internal
Pull-down
Input
Input
Power
Input
Internal
Pull-down
Input
Internal
Pull-down
Input
Input
Internal
Pull-down
Internal
Pull-down
Power
Output
Output
Output
Output
Power
Output
Output
Power
Output
Output
Power
Description
Differential clock input. Weak 100kohms internal pull-down.
Complementary differential clock input. Weak 100kohms internal pull-down.
Crystal Oscillator interface output.
Crystal Oscillator interface input, or single-ended LVCMOS clock input. Ensure that
the input voltage is 1.2V max. Refer to the section “Overdriving the XIN/REF
Interface”.
Analog functions power supply pin. Connect to 1.8V to 3.3V. VDDA and VDDD should
have the same voltage applied.
Input clock select. Selects the active input reference source in manual switchover
mode.
0 = XIN/REF, XOUT (default)
1 = CLKIN, CLKINB
CLKSEL Polarity can be changed by I2C programming as shown in Table 4.
Enables/disables the outputs (OE) or powers down the chip (SD). The SH bit
controls the configuration of the SD/OE pin. The SH bit needs to be high for SD/OE
pin to be configured as SD. The SP bit (0x02) controls the polarity of the signal to be
either active HIGH or LOW only when pin is configured as OE (Default is active
LOW.) Weak internal pull down resistor. When configured as SD, device is shut
down, differential outputs are driven high/low, and the single-ended LVCMOS
outputs are driven low. When configured as OE, and outputs are disabled, the
outputs can be selected to be tri-stated or driven high/low, depending on the
programming bits as shown in the SD/OE Pin Function Truth table.
Configuration select pin, or I2C SDA input as selected by OUT0_SEL_I2CB. Weak
internal pull down resistor.
Configuration select pin, or I2C SCL input as selected by OUT0_SEL_I2CB. Weak
internal pull down resistor.
Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for
OUT4/OUT4B.
Output Clock 4. Please refer to the Output Drivers section for more details.
Complementary Output Clock 4. Please refer to the Output Drivers section for more
details.
Complementary Output Clock 3. Please refer to the Output Drivers section for more
details.
Output Clock 3. Please refer to the Output Drivers section for more details.
Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for
OUT3/OUT3B.
Complementary Output Clock 2. Please refer to the Output Drivers section for more
details.
Output Clock 2. Please refer to the Output Drivers section for more details.
Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for
OUT2/OUT2B.
Complementary Output Clock 1. Please refer to the Output Drivers section for more
details.
Output Clock 1. Please refer to the Output Drivers section for more details.
Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for
OUT1/OUT1B.
MARCH 3, 2017
3
PROGRAMMABLE CLOCK GENERATOR
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