5P49V5901BDDDNLGI 查看數據表（PDF） - Integrated Device Technology

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5P49V5901BDDDNLGI

Programmable Clock Generator

Integrated Device Technology 

PLL Features and Descriptions

Spread Spectrum

To help reduce electromagnetic interference (EMI), the

5P49V5901 supports spread spectrum modulation. The

output clock frequencies can be modulated to spread energy

across a broader range of frequencies, lowering system EMI.

The 5P49V5901 implements spread spectrum using the

Fractional-N output divide, to achieve controllable modulation

rate and spreading magnitude. The Spread spectrum can be

applied to any output clock, any clock frequency, and any

spread amount from ±0.25% to ±2.5% center spread and

-0.5% to -5% down spread.

Table 2: Loop Filter

PLL loop bandwidth range depends on the input reference

frequency (Fref) and can be set between the loop bandwidth

range as shown in the table below.

Input Reference

Loop

Loop

Frequency–Fref Bandwidth Min Bandwidth Max

(MHz)

(kHz)

(kHz)

1

40

126

350

300

1000

5P49V5901 DATASHEET

If OUT0_SEL_I2CB was 0 at POR, alternate configurations

can only be loaded via the I2C interface.

Table 4: Input Clock Select

Input clock select. Selects the active input reference source in

manual switchover mode.

0 = XIN/REF, XOUT (default)

1 = CLKIN, CLKINB

CLKSEL Polarity can be changed by I2C programming as

shown in the table below.

PRIMSRC

0

0

1

1

CLKSEL

0

1

0

1

Source

XIN/REF

CLKIN, CLKINB

CLKIN, CLKINB

XIN/REF

PRIMSRC is bit 1 of Register 0x13.

Table 3: Configuration Table

This table shows the SEL1, SEL0 settings to select the

configuration stored in OTP. Four configurations can be stored

in OTP. These can be factory programmed or user

programmed.

OUT0_SEL_I2CB SEL1 SEL0 I2C REG0:7 Config

@ POR

Access

1

0

0

No

0

0

1

0

1

No

0

1

1

1

0

No

0

2

1

1

1

No

0

3

0

X

X

Yes

1

I2C

defaults

0

X

X

Yes

0

0

At power up time, the SEL0 and SEL1 pins must be tied to

either the VDDD/VDDA power supply so that they ramp with

that supply or are tied low (this is the same as floating the

pins). This will cause the register configuration to be loaded

that is selected according to Table 3 above. Providing that

OUT0_SEL_I2CB was 1 at POR and OTP register 0:7=0, after

the first 10mS of operation the levels of the SELx pins can be

changed, either to low or to the same level as VDDD/VDDA.

The SELx pins must be driven with a digital signal of < 300ns

Rise/Fall time and only a single pin can be changed at a time.

After a pin level change, the device must not be interrupted for

at least 1ms so that the new values have time to load and take

effect.

MARCH 3, 2017

5

PROGRAMMABLE CLOCK GENERATOR

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