AD7910 查看數據表（PDF） - Analog Devices
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AD7910 Datasheet PDF : 24 Pages
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AD7910/AD7920
TIMING SPECIFICATIONS
VDD = 2.35 V to 5.25 V, TA = TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter1
fSCLK 2
tCONVERT
tQUIET
AD7910/AD7920
Limit at TMIN, TMAX
10
5
14 × tSCLK
16 × tSCLK
50
Unit
kHz min3
MHz max
ns min
Description
AD7910
AD7920
Minimum quiet time required between bus relinquish and start of next
conversion
t1
t2
t3 4
t4
t5
t6
t75, 6
t86, 7
tPOWER-UP 8
10
10
22
40
0.4 × tSCLK
0.4 × tSCLK
10
9.5
7
36
See Note 7
1
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns min
ns max
ns min
μs max
Minimum CS pulse width
CS to SCLK setup time
Delay from CS until SDATA three-state disabled
Data access time after SCLK falling edge
SCLK low pulse width
SCLK high pulse width
SCLK to data valid hold time
VDD ≤ 3.3 V
3.3 V < VDD ≤ 3.6 V
VDD > 3.6 V
SCLK falling edge to SDATA three-state
SCLK falling edge to SDATA three-state
Power-up time from full power-down
1 Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
2 Mark/Space ratio for the SCLK input is 40/60 to 60/40.
3 Minimum fSCLK at which specifications are guaranteed.
4 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 1.8 V when VDD = 2.35 V and 0.8 V or 2.0 V for VDD > 2.35 V.
5 Measured with a 50 pF load capacitor.
6 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, shown in the Timing Specifications is the true bus relinquish
time of the part and is independent of the bus loading.
7 T7 values apply to t8 minimum values also.
8 See Power-Up Time section.
200μA
IOL
TO OUTPUT
PIN CL
50pF
1.6V
200μA
IOH
Figure 2. Load Circuit for Digital Output Timing Specifications
Rev. C | Page 6 of 24
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